This invention relates to integrated logic circuits; and in particular, it relates to structures for such circuits which improve their testability for defective via contacts.
Basically, an integrated logic circuit is a combination of hundreds or thousands of logic gates which are integrated on a single semiconductor chip. These gates are interconnected on the chip to perform various logic functions by conductors that are formed by one or more patterned metal layers.
The conductors are separated from the gates and separated from each other by insulating layers. Connections between the conductors and the gates are made by via contacts which penetrate through the insulating layers.
After the fabrication of the integrated logic circuit is complete, the chip is usually tested by applying a set of logic signals to the input terminals of the chip and examining the state of the output signals that are generated. This test typically is repeated hundreds of times with different combinations of input signals. However, regardless of how many different combinations of input signals are used, certain types of defects in the chip still are not detected.
In particular, the above described test does not detect whether or not the chip is operating at the correct speed. To check the speed of a circuit, the delay between the application of the input signals to the chip's input terminals and the generation of the output signals on the chip's output terminals must be measured. Simply checking that the output signals are in their correct state does not check speed.
However, a typical chip may have over one hundred terminals, and the delay through the chip for each of those terminals will be different depending upon the connections within the chip. Thus, to test the spped at which signals propagate from all the input terminals to all the output terminals under all combinations of input signals is not practicable.
Further, discrete wiring must be used to connect the input and output terminals of a chip to any tester, and such wiring can cause reflections and ringing to occur on the input and output signals. Consequently, even if the delay of all the output signals were separately measured for all combinations of input signals, the ringing and reflections caused by the discrete wiring would add to the delay and give a false indication of a defect.
One way in which a logic gate's speed can be adversely slowed down by a fabrication defect is with a defective via contact. This is especially true where the logic gate is of the type which has an output transistor that turns on and off depending upon whether or not the gate is in a logical one or a logical zero state, and has a pulldown resistor that is coupled to the output terminal through a via contact.
If the via contact is defective, the pulldown resistor is not connected to the output terminal. Then, when the output transistor turns off, the voltage on the output terminal does not quickly drop to the zero level; but instead, it slowly ramps down to a zero.
This type of defect is not detected by simply examining the state of the chip's output signals without measuring their speed. However, such a defect is intolerable in a system environment in which signal speed is critical.
Accordingly, a primary object of the invention is to provide an integrated logic circuit having improved testability for defective via contacts.